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EM250
2 Top-Level Functional Description
Figure 2 shows a detailed block diagram of the EM250.
TX_ACTIVE
PA select
Data
Program
RF_TX_ALT_P,N
RF_P,N
PA
PA
LNA
SYNTH
IF
DAC
ADC
MAC
+
Baseband
SRAM
5kB
XAP2b CPU
Flash
128kB
PacketTrace
Interrupt
Encryption
BIAS_R
Bias
controller
accelerator
General
OSCA
OSCB
HF OSC
Internal
purpose
timers
GPIO
registers
Always
powered
Watchdog
SIF
SIF_CLK
SIF_MISO
SIF_MOSI
RC-OSC
nSIF_LOAD
OSC32A
OSC32B
LF OSC
ADC
UART/
SPI/I2C
Chip
manager
Sleep
timer
VREG_OUT
nRESET
Regulator
POR
GPIO multiplexor swtich
GPIO[16:0]
Figure 2. EM250 Block Diagram
The radio receiver is a low-IF, super-heterodyne receiver. It utilizes differential signal paths to minimize noise
interference, and its architecture has been chosen to optimize co-existence with other devices within the
2.4GHz band (namely, IEEE 802.11g and Bluetooth). After amplification and mixing, the signal is filtered and
combined prior to being sampled by an ADC.
The digital receiver implements a coherent demodulator to generate a chip stream for the hardware-based
MAC. In addition, the digital receiver contains the analog radio calibration routines and control of the gain
within the receiver path.
The radio transmitter utilizes an efficient architecture in which the data stream directly modulates the VCO.
An integrated PA boosts the output power. The calibration of the TX path as well as the output power is
controlled by digital logic. If the EM250 is to be used with an external PA, the TX_ACTIVE signal should be used
to control the timing of the external switching logic.
The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24MHz crystal with its loading
capacitors is required to properly establish the PLL reference signal.
The MAC interfaces the data memory to the RX and TX baseband modules. The MAC provides hardware-based
IEEE 802.15.4 packet-level filtering. It supplies an accurate symbol time base that minimizes the
synchronization effort of the software stack and meets the protocol timing requirements. In addition, it
provides timer and synchronization assistance for the IEEE 802.15.4 CSMA-CA algorithm.
120-0082-000V Rev 1.1
Page 10
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